Continued scaling in semiconductor technology increases marginalities, variabilities, and challenges in manufacturing. Further, continued scaling in poly pitches between devices results in a shrinking space where several implant processes, stress memorization techniques, silicidation, dual stress liner formation and strained contact formation must occur.
Modern integrated circuits use several poly pitches depending on their device gate lengths. To ensure proper device targeting, conformal spacer materials must be deposited. However, the use of conformal spacers results in certain drawbacks, including performance degradation and increased effort in manufacturing. Further, multiple spacer formations for a device results in less space for implantation, silicidation, and contact formation as the poly pitch decreases. Typically, after spacer formation a protection layer is formed to protect the P poly and diffusion resistors from silicide formation. With the reduced available space, formation of the protection layer is difficult and often results in unwanted residuals that prevent appropriate silicide formation and cause yield fallout.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with improved silicide contacts. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with non-conformal silicidation spacers. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.